when "00011100"=> d<="00001000" ; when "00011101"=> d<="00000100" ;
when "00011110"=> d<="00000001" ;when "00011111"=> d<="00000000" ;
when "00100000"=> d<="00000000" ; when "00100001"=> d<="00000001" ;
when "00100010"=> d<="00000100" ;when "00100011"=> d<="00001000" ;
when "00100100"=> d<="00001101" ; when "00100101"=> d<="00010011" ;
when "00100110"=> d<="00011010" ;when "00100111"=> d<="00100010" ;
when "00101000"=> d<="00101011" ; when "00101001"=> d<="00110101" ;
when "00101010"=> d<="01000000" ;when "00101011"=> d<="01001011" ;
when "00101100"=> d<="01010111" ; when "00101101"=> d<="01100011" ;
when "00101110"=> d<="01110000" ;when "00101111"=> d<="01111100" ;
when "00110000"=> d<="10001001" ; when "00110001"=> d<="10010110" ;
when "00110010"=> d<="10100010" ;when "00110011"=> d<="10101110" ;
when "00110100"=> d<="10111010" ; when "00110101"=> d<="11000101" ;
when "00110110"=> d<="11001111" ;when "00110111"=> d<="11011001" ;
when "00111000"=> d<="11100001" ; when "00111001"=> d<="11101001" ;
when "00111010"=> d<="11101111" ;when "00111011"=> d<="11110101" ;
when "00111100"=> d<="11111001" ; when "00111101"=> d<="11111100" ;
when "00111110"=> d<="11111110" ;when "00111111"=> d<="11111111" ;
when others=> null;
end case;
end if;
end process;
p180<='1';
end behav;
,多功能波形发生器VHDL程序与仿真