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SST89C58电子盘电路及代码

03-19 02:35:27 | http://www.5idzw.com | 单片机电路图 | 人气:300
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;========================================
        
main:        acall Write_Sctr

        acall Read_Sctr

        acall Compare

        jb      F0, fail

        clr     P1.4              ; indicates successful operations.
        setb  P1.5
        sjmp  $

fail:                clr     P1.5              ; flags failed comaprison.
        setb  P1.4
        sjmp  $
;========================================

Function:    acall  Busy

        mov  dptr, #Sectr_Cnt
        mov  a, R2                    ; R2 is Sector Count
        movx @dptr, a
        
        mov  dptr, #Sectr_No
        mov  a, R3                ; R3 contains LBA0:7
        movx @dptr, a

        mov  dptr, #Cylinder_Low
        mov  a, R4                ; R4 contains LBA8:15
        movx @dptr, a

        mov  dptr, #Cylinder_Hi
        mov  a, R5                 ; R5 contains LBA16:23
        movx @dptr, a

        mov  dptr, #Drv_Head
        mov  a, R6                 ; R6 contains LBA24:27
        anl    a,    #00001111b
        orl     a,    #11100000b   ; bit4=0 as MASTER, 1 as Slave; bit6=1, enable LBA.
        movx @dptr, a
    
        mov  dptr, #command
        mov  a, R7                     ; R7 is command code.
        movx @dptr, a
        ret

;========================================

Busy:             mov  dptr, #status
        movx a, @dptr
        jb   acc.7, Busy
               jb   acc.0, errors
;        jnb  acc.6, Busy
        clr  a                        ; acc=0 when successful
        clr  C                        ; C=0, ADC is not busy (BUSY=0) and no error (ERR=0)
        ret            ; and is ready to accept commands (RDY=1)

errors:           mov  dptr, #Error_Reg
        movx a, @dptr
        setb C                      ; C=1 flags error codes contained in ACC register
        ret

;========================================

WaitDRQ:      mov  dptr, #status
        movx a, @dptr
        jb   acc.7,  WaitDRQ     ; if BUSY=1, then WaitDRQ
        jnb  acc.3, WaitDRQ     ; if DRQ=0, then WaitDRQ
               jb   acc.0,  errors           ; if ERR=1, then read errors code and set flag C
;        jnb  acc.6, WaitDRQ
        clr  a
        clr  C                             ; C=0, ADC is BUSY=0, DRQ=1, ERR=0.
        ret             

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